This invention relates to a design layout method for metal lines of an integrated circuit (IC), and more particularly relates to a method of spacing metal lines in an integrated circuit to minimize capacitive issues along speed sensitive pathways in a random access memory structure to reduce signal delay without negatively impacting the Werner Fill process.
The Werner Fill process is disclosed by commonly owned U.S. Pat. No. 5,981,384, the disclosure of which is herein fully incorporated by reference. The Werner Fill process modifies the layout of electrically unisolated or live metal lines so that the spacing between the metal lines is substantially standardized prior to performing deposition of an intermetal dielectric layer (IDL). According to the Werner Fill process, circuit layout design modifications are made by adding dummy metal line features in areas of the layout having open spaces between parallel metal lines, and adding metal line spacers to existing metal lines to reduce the spacing therebetween to a standardized spacing or gap. As the nonstandard spacing between metal lines becomes standardized to the standardized spacing or gap, an intermetal dielectric deposition results in a planarized surface of the intermetal dielectric. Consequently, many conventional process steps for planarizing the intermetal dielectric can be skipped or simplified.
However, as semiconductor device geometries continue to decrease in size, providing more devices per fabricated wafer, capacitance between metal line features (dummy and/or live) becomes an issue. Currently, some devices are being fabricated with spacing between metal line features of less than about 0.25 xcexcm, and in some cases, the spacing between metal line features is as little as about 0.11 xcexcm. Since delay of a signal through a metal line is directly proportional to capacitance, and capacitance is inversely proportional to spacing, further reductions in spacing will cause increases in capacitance, and thus substantial signal delay. This increased signal delay along long, substantially parallel metal lines features, which typically are speed sensitive pathways, has noticeably affected the other desire in the art to provide faster semiconductor devices. Accordingly, a need still exists to minimize capacitive issues (i.e., increased capacitance) along steed sensitive pathways in a random access memory structure to reduce signal delay without negatively impacting the Werner Fill process.
The inventive process enhances metal line layout designs by providing two separate control spaces for the Werner Fill process along speed sensitive pathways. Speed sensitive pathways are defined by long, substantially parallel metal lines that typically extending over 10 xcexcm in length. One control space (i.e.,DRCgap1) is for decreasing the spacing between various metal features to standardize such spacing according to the Werner Fill process. A second control space (i.e., DRCgap2) is for addressing capacitance issues along speed sensitive pathways. For example, for a speed sensitive pathway where there are two long parallel adjacent metal lines, the Werner Fill process would bring the space between these lines down to a space defined by DRCgap1 by adding metal line features or spacers. Instead, according to the present invention, the added metal line features or spacers provide a fundamental space between these lines of DRCgap2, which is defined to be somewhere between DRCgap1 and the maximum space that will still be readily fillable with IDL, and thus without negatively impacting the Werner Fill process. At the ends of the long parallel metal lines, the spacing of the added metal line features, or spacers, is reduced to the first control spacing DRCgap, in order to best fill the three-way-intersections (TWIs) with subsequent dielectric depositions.
After the IC structure has been designed to minimize the spacing and capacitance between nearest parallel metal lines according to the inventive process, a deposition of an intermetal dielectric layer is made. Although the present invention is not limited to specific advantages or functionality, it is noted that the present inventive process provides for the IC structure""s substantial planarization due to the uniform spacing between metal features beneath the intermetal dielectric layer with the first control spacing DRCgap1. Further, the present inventive process addresses capacitance issues along speed sensitive pathways of the IC structure due to providing a second control spacing DRCgap2 between long parallel metal lines.